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s 6 nc dual-in-line s 3 s 5 v+ en v s 14 a 2 s 15 s 1 a 3 s 12 s 10 1 2 3 4 5 6 7 8 28 27 26 25 24 s 16 23 22 21 top view s 8 9 s 2 20 s 9 a 0 a 1 10 s 7 19 nc s 13 11 nc 12 s 11 18 17 gnd 13 16 14 15 d s 4 decoders/drivers a 0 a 2 s 1b v+ s 5b s 1a a 1 nc d b nc v dual-in-line s 2a s 7a s 6a s 8a s 4b s 7b en d a s 3b s 8b s 5a s 2b gnd s 3a nc s 4a s 6b 1 2 3 4 5 6 7 8 28 27 26 25 24 23 22 21 top view 920 10 19 11 12 18 17 13 16 14 15 decoders/drivers dg506a_mil dg507a_mil dg506a_mil/507a_mil vishay siliconix document number: 70066 s-00405erev. d, 21-feb-00 www.vishay.com faxback 408-970-5600 5-1 single 16-ch/differential 8-ch cmos analog multiplexers (obsolete for non-hermetic. use dg406/407 as pin-for-pin replacements.) low on-resistance: 240 ttl and cmos logic compatible low power: 30 mw break-before-make switching 44-v power supply rating transition time: 600 ns easily interfaced low power consumption low system crosstalk wide analog signal range communication systems ate data acquisition systems audio signal routing and multiplexing medical instrumentation a channel in the on state conducts current equally well in both directions. in the off state each channel blocks voltages up to the power supply rails, normally 30 v peak-to-peak. an enable (en) function allows for device selection when several multiplexers are used. all control inputs, address (a x ) and enable (en) are ttl or cmos compatible over the full specified operating temperature range. the dg506a_mil/507a_mil are fabricated in the vishay siliconix plus-40 process, which includes improved esd protection for ruggedness. an epitaxial layer prevents latch up. the dg506a_mil/507a_mil are available in hermetic packages. for plastic packages, use the dg406/407 as pin-for-pin replacements. for wideband/video multiplexing, the dg536 is recommended.

dg506a_mil/507a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-2 document number: 70066 s-00405erev. d, 21-feb-00
a 3 a 2 a 1 a 0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16
temp range package part number 55 125 c 28 - pin cerdip dg506aak 55 to 125 c 28 - pin cerdip dg506aak/883 55 to 125 c 28-pin sidebraze jm38510/19001bxc lcc-28* dg506aaz/883 *block diagram and pin configuration not shown. a 2 a 1 a 0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 logic a0o = v al 0.8 v logic a1o = v ah 2.4 v x = don't care
temp range package part number 55 125 c 28 - pin cerdip dg507aak 55 to 125 c 28 - pin cerdip dg507aak/883 55 to 125 c 28-pin sidebraze jm38510/19003bxc 28-pin lcc dg507aaz/883 voltage referenced to v v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a , v s , v d (v) 2 v to (v+) +2 v or . . . . . . . . . . . . . . . . . . . . . . . . 20 ma, whichever occurs first current (any terminal, except s or d) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current, s or d 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 40 ma . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature (cerdip) 65 to 150 c . . . . . . . . . . . . . . . . . . . . (plastic dip) 65 to 125 c . . . . . . . . . . . . . . . . power dissipation (package) b 28-pin cerdip and sidebraze 1200 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-pin plcc no tag 1200 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lcc-20,28 c 1000 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads soldered or welded to pc board. c. derate 14 mw/ c above 75 c.
dg506a_mil/507a_mil vishay siliconix document number: 70066 s-00405erev. d, 21-feb-00 www.vishay.com faxback 408-970-5600 5-3
test conditions unless otherwise specified a suffix 55 to 125 c parameter symbol v+ = 15 v, v = 15 v v in = 2.4 v, 0.8 v f temp b min d typ c max d unit analog switch analog signal range e v analog full 15 15 v drain-source on-resistance r ds(on) v d = 10 v, i s = 200 a room full 240 400 500 r ds(on) matching g r ds(on) 10 v < v s < 10 v room 6 % source off leakage current i s(off) v s = 10 v, v d = 10 v v en = 0 v room full 1 50 1 50 a drain off i d(off) v d = 10 v v s = 10 v dg506a_mil room full 10 300 10 300 a drain off leakage current i d(off) v s = 10 v v en = 0 v dg507a_mil room full 5 200 5 200 na drain on i d(on) v s =v d = 10 v dg506a_mil room full 10 300 10 300 drain on leakage current i d(on) v s = v d = 10 v dg507a_mil room full 5 200 5 200 digital control logic input current itvlt hih i ah v a = 2.4 v room full 10 30 gp input voltage high i ah v a = 15 v room full 10 30 a logic input current input voltage low i al v en = 0 v, 2.4 v, v a = 0 v room full 10 30 dynamic characteristics transition time t trans see figure 2 room 0.6 1.0 break-before-make time t open see figure 4 room 0.2 s enable turn-on time t on(en) see figure 3 room 1 1.5 s enable turn-off time t off(en) s ee fi gure 3 room 0.4 1.0 charge injection q room 6 pc off isolation h oirr v en = 0 v, r l = 1 k , c l = 15 pf v s = 7 v rms , f = 500 khz room 68 db source off capacitance c s(off) v en = 0 v, v s = 0 v, f = 140 khz room 6 f drain off capacitance c d(off) v en = 0 v v d =0v dg506a_mil room 45 pf d ra i n of f c apac it ance c d(off) v d = 0 v f = 140 khz dg507a_mil room 23 p power supplies positive supply current i+ v en = 0 v , v a = 0 v room 1.3 2.4 ma negative supply current i v en = 0 v , v a = 0 v room 1.5 0.7 ma notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function. g. r ds(on) r ds(on) max r ds(on) min r ds(on) ave h. off isolation 20 log v d v s ,v s input to off switch, v d output due to v s .
dg506a_mil/507a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-4 document number: 70066 s-00405erev. d, 21-feb-00
r ds(on) vs. v d and power supply input switching threshold vs. v+ and v supply voltages supply current vs. switching frequency crosstalk vs. frequency charge injection vs. analog voltage r ds(on) vs. v d and temperature r ds(on) drain-source on-resistance ( (v) t v q (pc) r ds(on) drain-source on-resistance ( (db) talk x v d drain voltage (v) v+, v positive and negative supplies (v) v d drain voltage (v) v s source voltage (v) f frequency (hz) f frequency (hz) i+, i (ma) 15 15 2.5 2.0 1.5 1.0 0.5 0 400 16 15 10 5 0 5 10 14 12 10 8 6 4 2 0 350 300 250 200 150 100 50 0 10 5 0 5 10 15 125 c 600 20 10 0 10 20 500 400 300 200 100 v+ = 15 v v = 15 v v+ = 15 v v = 15 v 0 6 4 2 0 2 4 6 v+ = 15 v v = 15 v 100 k 10 k 1 m 0 20 40 60 80 100 120 1 k 1 m 10 m 10 k 100 k cerdip plastic v+ = 15 v v = 15 v ref. 0.0 dbm o10 5 v 7.5 v 10 v 15 v 20 v o5 o15 o20 i i+ 25 c 55 c ) w ) w
dg506a_mil/507a_mil vishay siliconix document number: 70066 s-00405erev. d, 21-feb-00 www.vishay.com faxback 408-970-5600 5-5
off isolation vs. frequency switching time vs. temperature i s(off) vs. analog voltage i d(on) , i d(off) vs. analog voltage switching time vs. positive supply voltage leakages vs. temperature (pa) i d (pa) i s leakage current (ns) t trans , t open (ns) t trans , t open oirr (db) f frequency (hz) temperature ( c) v+ positive supply (v) temperature ( c) v s source voltage (v) v d drain voltage (v) 0 20 40 60 80 100 120 1 k 1 m 10 m 10 k 100 k cerdip plastic v+ = 15 v v = 15 v ref. 0 dbm i d(off) i d(on) v+ = 15 v v = 15 v t a = 25 c 20 0 20 40 60 80 15 10 5 0 5 10 15 1000 55 800 600 400 200 35 15 5 25 45 65 105 125 85 t rans t open 1100 10 12 14 16 18 20 22 1000 900 800 700 600 500 400 300 200 v+ = 15 v v = 15 v v d = 14 v i d(on) , i d(off) i s(off) 100 na 10 na 1 na 100 pa 10 pa 1 pa 0.1 pa 55 35 15 5 25 45 65 85 105 125 t rans t open v+ = 15 v v = 15 v 900 700 500 300 15 10 5 5 15 15 10 5 0 5 10 15 10 0 v+ = 15 v v = 15 v v s = v d t a = 25 c i s(off)
dg506a_mil/507a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-6 document number: 70066 s-00405erev. d, 21-feb-00

figure 1. v+ en v v+ v v+ a x v+ v+ v v a 0 gnd decode/ drive s 1 s n d v+ v + v v+ + +

figure 2. transition time logic input switch output v s8 v o t trans t r <20 ns t f <20 ns s 8 on s 1 on t trans 0 v v s1 50% 90% 90% 3 v 0 v dg506a_mil s 1b s 8b a 2 d b a 1 * a 0 * = s 1a s 8a , s 2b s 7b , d a 50 1 m v o +2.4 v +15 v 15 v en v+ v gnd 35 pf s 1 s 2 s 15 s 16 a 2 a 1 a 0 50 1 m v o a 3 10 v 10 v +2.4 v +15 v 15 v en v+ v gnd d 35 pf dg507a_mil 10 v 10 v
dg506a_mil/507a_mil vishay siliconix document number: 70066 s-00405erev. d, 21-feb-00 www.vishay.com faxback 408-970-5600 5-7 figure 3. enable switching time v o 10% t r <20 ns t f <20 ns v o logic input t on(en) 90% switch output 50% t off(en) 3 v 0 v 0 v a 1 50 a 0 s 1 v o a 2 5 v +15 v 15 v 1 k en s 2 s 16 v+ v gnd d 35 pf a 3 v o s 1b a 2 s 1a s 8a s 2b s 8b a 1 d a and d b a 0 50 1 k +15 v 15 v en v+ v gnd 35 pf dg506a_mil dg507a_mil 5 v figure 4. break-before-make interval 50% 80% logic input switch output v o v s t open t r <20 ns t f <20 ns 0 v 3 v 0 v 50 a 0 all s and d a 1 k a 3 d,d b a 1 a 2 +2.4 v +15 v 15 v en v+ v v o gnd +5 v 35 pf dg506a_mil dg507a_mil
dg506a_mil/507a_mil vishay siliconix www.vishay.com faxback 408-970-5600 5-8 document number: 70066 s-00405erev. d, 21-feb-00
v+ positive supply voltage (v) v negative supply voltage (v) v in logic input voltage v inh(min) /v inl(max) (v) v s or v d analog voltage range (v) 15 b 12 10 8 c 15 12 10 8 2.4/0.8 2.4/0.8 2.2/0.6 2.0/0.5 15 to 15 12 to 12 10 to 10 8 to 8 notes: a. application hints are for design aid only, not guaranteed and not subject to production testing. b. electrical parameter chart based on v+ = 15 v, v = 15 v. c. operation below 8 v is not recommended due to shift in v inl(max) . overvoltage protection a very convenient form of overvoltage protection consists of adding two small signal diodes (1n4148, 1n914 type) in series with the supply pins (see figure 5). this arrangement effectively blocks the flow of reverse currents. it also floats the supply pin above or below the normal v+ or v value. in this case the overvoltage signal actually becomes the power supply of the ic. from the point of view of the chip, nothing has changed, as long as the difference between v s and the v rail doesn't exceed +44 v. the addition of these diodes will reduce the analog signal range to 1 v below v+ and 1 v above v, but it preserves the low channel resistance and low leakage characteristics. 1n4148 dg506a_mil v +v 1n4148 internal junction internal junction figure 5. overvoltage protection using blocking diodes v+ v g v s x v g +v v dg507a_mil figure 6. a 32-channel data acquisition system a 0 a 1 a 2 a 3 channel 1 channel 2 channel 16 dg506a_mil #1 en a 0 a 1 a 2 a 3 channel 17 channel 18 channel 32 dg506a_mil #2 en d dg419 a s/h a/d data bus controller d
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.

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